The development of ever more advanced microprocessors and associated bus architectures continues at a rapid pace. For example, Intel Corporation of Santa Clara, Calif., recently introduced their latest processor, the Pentium.RTM.Pro at a time when the market demand for the previous generation Pentium.RTM. processor was still expanding. The Pentium.RTM.Pro processor offers a great boost in performance over the previous generation Pentium.RTM. processor and it introduces a new high-performance, pipelined system bus architecture.
A dilemma arises for computer system developers who wish to design systems based on the latest bus architecture, but who still wish to accommodate processor designs based upon previous generation processors, or processors having alternate bus architectures. For instance, many system designers would like to design their computer systems so as to be compatible with Intel's new Pentium.RTM.Pro bus--to take advantage of state-of-the-art features--but who still must meet the current market demand for compatibility with the Pentium.RTM. processor architecture. This generally means that the system processor must have the same pinout and/or operate in accordance with the bus architecture designed for the Pentium.RTM. processor.
Unfortunately, the bus signaling protocol of the Pentium.RTM.Pro processor differs significantly from the bus signaling protocol of the Pentium.RTM. processor. As a result, system developers have been left with the unsavory choice of either maintaining compatibility with mainstream processor designs--while foregoing the advantages associated with a state-of-the-art bus architecture--or, designing their system in accordance with the signaling protocol of the advanced bus architecture of the Pentium.RTM.Pro processor--at the expense of reduced market acceptability due to the broader customer base for Pentium.RTM. processor-based systems. Therefore, what is needed, is a computer system architecture which is adapted for use with a variety of processor types, with each processor type potentially employing an alternate bus architecture.
As will be seen, the present invention overcomes the problems inherent in the prior art by providing a universal computer architecture that includes a processor subsystem (or module) coupled to a host through a standardized computer bus interface. The invention offers compatibility with a wide variety of processor types while obviating the need to modify basic system architecture. The present invention advantageously allows a previous generation processor (e.g., a Pentium.RTM. processor) to transfer information to/from other agents coupled to the high-performance (i.e., Pentium.RTM.Pro processor) system bus in a seamless manner.